The present invention relates to a clock generation circuit for generating a clock signal which is used for reproducing a signal on a recording medium.
In recent years, a signal processing which is called PRML (partial response maximum likelihood) is increasingly introduced into data reproduction signal processings in digital recording and reproducing apparatus. In this data reproduction signal processing, signals are processed digitally and clock generation itself is also changing from a conventional analog PLL (phase locked loop) to a digital PLL. While the introduction of the PRML is advanced in HDDs (hard disk drives), the PRML has not been introduced into optical disk apparatuses yet. A clock generation circuit has no problem as long as it is used in the HDDs, but it has problems when used in optical disk apparatuses.
Disks like a CD (compact disk) or a DVD (digital versatile disk) are produced for CLV (constant linear velocity) reproduction use, but in reality they are reproduced also at CAV (constant angular velocity) or they require jitter-free reproduction for reading data before a spindle rotating speed reaches the CLV. Consequently, the CD or DVD requires a performance for executing the PLL continuously in a wider frequency range than that of the HDD.
For optical disks such as the CD or DVD, a binary discriminator with an analog comparator is used for data determination. In addition, the analog PLL is used for generating a timing clock for the determination. The signal processing for the CD or DVD is usually performed in an analog fashion and thus called an analog read channel. On the other hand, the signal processing method which is called PRML is introduced to determine data in recent digital recording devices such as the HDD. In the PRML, data is determined with digital values and the signal processing is also performed digitally, and thus it is called a digital read channel. In the digital read channel, the digital PLL is used for generating a timing clock for the discrimination.
The digital PLL which is used in the HDD or the like will be described as a prior art. FIG. 15 is a block diagram illustrating a structure of a reproduction apparatus including a clock generation circuit 1000 according to a conventional digital PLL system.
The clock generation circuit 1000 comprises a master PLL 1100, a phase comparator 4, a loop filter 5, a minute control D/A converter 6, and a slave VCO 1106. The master PLL 1100 comprises a 1/N frequency divider 1101, a phase comparator 1102, aloop filter 1103, a master VCO 1104, and a 1/M frequency divider 1105.
A reading head 2 reads an analog signal from a recording medium 1.
An A/D converter 3 converts the read analog signal into a digital signal in synchronization with a clock signal supplied by the clock generation circuit 1000, and outputs the digital signal to a reproduction circuit (not shown) which outputs digital data as a reproduction signal, and to the phase comparator 4 in the clock generation circuit 1000.
The phase comparator 4 extracts a phase error of the digital signal in synchronization with a sampling clock signal generated by the clock generation circuit 1000, and outputs the phase error to the loop filter 5.
The loop filter 5 filters the phase error to convert the same into a digital oscillation instruction signal, and outputs the signal to the minute control D/A converter 6.
The minute control D/A converter 6 converts the digital oscillation instruction signal into an analog oscillation instruction signal of an analog voltage proportional to the digital oscillation instruction signal, and outputs the analog signal to the slave VCO 1106.
The slave VCO 1106 has a wide oscillation range and its setting of an oscillation frequency is controlled in two steps, so as to generate a clock which is completely locked. That is, the master PLL 1100 sets a rough frequency of the oscillation range of the slave VCO 1106 and the minute control D/A converter 6 performs a fine adjustment of the frequency.
The 1/N frequency divider 1101 frequency-divides a REF clock by N and the phase comparator 1102 matches phases of the 1/N-frequency REF clock and a signal which is frequency-divided by M with the 1/M frequency divider 1105 with each other, thereby constituting a PLL synthesizer. The 1/M frequency divider 1105 frequency-divides a signal output from the master VCO 1104, by M.
The loop filter 1103 filters a signal output from the phase comparator 1102, and outputs the signal to the master VCO 1104 and to the slave VCO 1106.
In the HDD, the disk rotating speed is fixed and the closer to the perimeter, the higher the linear velocity is. In order to increase the liner recording density in this situation, a method which is called xe2x80x9czone bit recordingxe2x80x9d is used for the HDD. The zone bit recording is a method for dividing a disk into several zones and recording data with varying recording rates. That is, since the recording rate is higher at an outer zone and lower at an inner zone, the center frequency of the clock signal which is output from the clock generation circuit should be changed according to zones. Accordingly, the master PLL 1100 changes the parameters of N and M, controls the oscillation frequency of the master VCO 1104, and sets the center frequency of the slave VCO 1106.
That is, the master PLL 1101 roughly sets the oscillation frequency of the slave VCO 1106 to a frequency which is near the center frequency of a signal which is to be reproduced (rough control), and generates a clock which is completely locked to the reproduction signal with the minute control D/A converter 6 (minute control).
In addition, Japanese Published Patent Application No. Hei. 7-78422 discloses a clock extraction circuit which creates a phase error signal from digital data after performing the AD conversion, by using a delay line.
However, the conventional digital PLL system cannot executes the PLL continuously at a switching point of the rough control.
The conventional digital PLL system has no problem when reading data which is zone-bit-recorded at CAV (constant angular velocity), at CAV, like the HDD. However, in the CAV reproduction of reading data which is recorded at CLV (constant linear velocity), at CAV or the jitter-free reproduction of reading data before the spindle has the speed of CLV, like optical disks such as the DVD, the center frequency of the reproduction signal is continuously changed. Therefore, the PLL is required to continuously follow the frequency within a center frequency changing range. However, the conventional digital PLL cannot follow the frequency continuously. That is, in the conventional digital PLL system, the switching point of the rough control is a discontinuous point and thus the continuity of the PLL cannot be maintained.
In the conventional digital PLL system, the division ratios N and M of the synthesizer should be changed at the rough adjustment of the frequency. When N and M are changed, it is difficult to switch the parameters of N and M at the same timing. Besides, even when the parameters of N and M can be switched simultaneously, the center frequency is largely shifted at the switching as well as the continuity of the oscillation phase is lost. As a result of the shifting of the center frequency at the rough adjustment switching, the control cannot be executed by the PLL for performing the minute adjustment, whereby the phase lock is taken off. When the phase lock is taken off, a clock cannot be generated and thereby data cannot be reproduced either.
As described above, even when the conventional digital PLL used for the HDD is applied to optical disks such as the DVD, it cannot execute the PLL continuously to the wide frequency range which is required for the CAV reproduction or the CLV jitter-free reproduction.
The present invention is made to solve the above problems and it is an object of the present invention to provide a clock generation circuit which can lock a wide frequency range continuously.
In order to attain the above object, a clock generation circuit according to the present invention comprises a following construction:
A clock generation circuit for generating a clock signal which is used for reproducing a signal from a recording medium, comprises a phase comparator for extracting a phase error signal from a digital signal which is obtained by converting an analog signal which is read from the recording medium; a loop filter for filtering the phase error signal; a minute control D/A converter for converting the signal filtered by the loop filter, into an analog signal; a range detector for detecting whether the signal filtered by the loop filter is above, below, or within a preset range; a modulation reference signal generator for generating a modulation reference signal when the signal filtered by the loop filter is above or below the range; a pulse width modulator for converting the modulation reference signal into a pulse train; an adder for adding a predetermined frequency set value and the signal converted by the pulse width modulator; a rough control D/A converter for converting a signal obtained by the adder, into an analog signal; a low-pass filter for cutting high-band components of the analog signal which is converted by the rough control D/A converter; an analog adder for adding the analog signal which is output from the minute control D/A converter, and the analog signal which passed the low-pass filter; and a voltage controlled oscillator for generating a clock signal at a frequency proportional to the signal which is obtained by the analog adder when the range detector detects that the signal filtered by the loop filter is above or below the range, and generating a clock signal at a frequency proportional to the signal which is obtained by the minute control D/A converter when the range detector detects that the signal filtered by the loop filter is within the range.
The pulse width modulator is constituted by delta sigma modulation.
According to the clock generation circuit of the present invention, the input overrange of the minute control D/A converter is detected by the range detector, the modulation reference signal is generated, and the pulse width modulation processing is performed, whereby the input voltage of the voltage controlled oscillator can be controlled more than the resolution of the rough control D/A converter. Even when the input range of the minute control D/A converter almost exceeds the preset range and the rough control D/A converter is changed, the present invention provides a clock generation circuit which can continuously perform good clock generation without PLL being taken off and continuously lock a wide frequency range, and provides a clock generation circuit which can continuously perform clock reproduction over all controllable frequency region.
In addition, a clock generation circuit according to the present invention comprises a following construction:
A clock generation circuit for generating a clock signal which is used for reproducing a signal from a recording medium, comprises a phase comparator for extracting a phase error signal from a digital signal which is obtained by converting an analog signal which is read from the recording medium; a loop filter for filtering the phase error signal; an oversampler for zero-pad oversampling the signal filtered by the loop filter; an interpolator for interpolating data which is zero-pad oversampled by the oversampler; a multivalued delta sigma modulator for converting the signal interpolated by the interpolator, into a multivalued delta sigma modulation signal; a rough control D/A converter for converting the multivalued delta sigma modulation signal, into an analog signal; a low-pass filter for cutting high-band components of the analog signal which is output from the rough control D/A converter; and a voltage controlled oscillator for outputting a clock signal at a frequency proportional tothe signal which passed the low-pass filter.
Therefore, according to the present invention, the loop filter signal is zero-pad oversampled, interpolated, and further multivalued delta sigma modulated, whereby the input voltage of the voltage controlled oscillator can be controlled more than the resolution of the rough control D/A converter. Consequently, a clock generation circuit which continuously locks a wide frequency range can be provided. Further, the minute control D/A converter is not required and only the rough control D/A converter is provided, whereby the structure is simplified.
Further according to the present invention, the modulation signal which changes smoothly and stably can be output from the pulse width modulator or the multivalued delta sigma modulator.